In a method for forming multilayered interconnects in formation process for semiconductor devices, with respect to a generation of a design rule of 130 nm or less, a damascene method in which a concave portion (a via hole or an interconnect groove) is formed in an insulating film, the concave portion is filled with a metal film principally by a metal plating method and the metal film is planarized by chemical mechanical polishing (CMP) is employed for forming a buried interconnect. In this case, as a method for forming a concave portion in an insulating film, apart from conventionally known dry etching, nano-imprint lithography proposed by S. Y. Chou, et al. in Non-patent Document 1 (Applied Physics Letter, Volume 67 (1995), pp. 3114-3116) or Patent Document 1 (U.S. Pat. No. 5,772,905 (1998, Jun. 30)) is known.
Now, a conventional pattern formation method by using the nano-imprint lithography will be described with reference to FIGS. 17A through 17E.
First, as shown in FIG. 17A, a film 102A of a thermosetting resin is formed on a substrate (semiconductor wafer) 101 in a surface portion of which devices such as transistors and interconnects (not shown in the drawing) have been formed, and thereafter, as shown in FIG. 17B, a pressing face of a mold 103 having a convex portion 104 on the pressing face is pressed against the film 102A, so as to transfer the convex portion 104 of the mold 103 onto the film 102A.
Next, as shown in FIG. 17C, with a pressure applied to the mold 103, the substrate 101 is annealed for curing the film 102A, so as to form a cured film 102B. In the case where the film 102A is made of a photo-setting resin, the cured film 102B is formed through irradiation with light of UV or the like with a pressure applied to the mold 103.
Then, as shown in FIG. 17D, the mold 103 is moved away from the cured film 102B, and thus, a concave portion 105 is formed in the cured film 102B through the transfer of the convex portion 104 of the mold 103.
Next, the whole cured film 102B is subjected to anisotropic dry etching (anisotropic etch back), so as to remove a portion of the cured film 102B remaining on the bottom of the concave portion 105 as shown in FIG. 17E.
S. Y. Chou et al. use PMMA (polymethyl methacrylate), that is, a resist material, as the material for the film 102A, and after curing the PMMA once, the concave portion 105 is formed by pressing the mold 103 against the film 102A with the PMMA slightly softened through annealing at 200° C. In this case, since the PMMA has been cured, a high pressure as high as 140 atmospheric pressures is disadvantageously necessary for forming the concave portion 105.
Therefore, in order to overcome this disadvantage, according to Patent Document 2 (Japanese Laid-Open Patent Publication No. 2000-194142), a photo-setting material film made of a liquid photo-setting material is used as the film 102A and the film 102A is cured through annealing and light irradiation with the mold 103 pressed against the film 102A. Thus, the applied pressure is reduced to several atmospheric pressures, and hence, the accuracy in horizontal positions of the mold 103 and the substrate 101 is improved.
At this point, a method for forming a buried interconnect included in multilayered interconnects by the damascene method will be described. In general, a method for forming a buried plug or a buried interconnect alone by the damascene method is designated as a single damascene method, and a method for forming both a buried plug and a buried interconnect simultaneously by the damascene method is designated as a dual damascene method.
Now, a formation method for a semiconductor device in which a plug or a metal interconnect is formed by the single damascene method will be described with reference to FIGS. 18A through 18E.
First, as shown in FIG. 18A, an insulating film 112 of, for example, a silicon oxide film is formed on a substrate (semiconductor wafer) 111 by, for example, a chemical vapor deposition (CVD) method or a spin on dielectric (SOD) method.
Next, as shown in FIG. 18B, a resist pattern 113 having an opening for forming a via hole or an interconnect groove is formed on the insulating film 112 by lithography. Thereafter, as shown in FIG. 18C, the insulating film 112 is dry etched by using the resist pattern 113 as a mask, thereby forming a concave portion 114 corresponding to a via hole or an interconnect groove in the insulating film 112.
Then, as shown in FIG. 18D, after forming a barrier metal layer (not shown in the drawing) by, for example, a sputtering method, a copper film 115 is deposited on the barrier metal layer by, for example, a plating method.
Next, as shown in FIG. 18E, an unnecessary portion of the copper film 115, namely, a portion thereof exposed above the insulating film 112, is removed by chemical mechanical polishing (CMP), so as to form a plug or metal interconnect 116 made of the copper film 115.
Now, a formation method for a semiconductor device in which a plug and a metal interconnect are formed by the dual damascene method will be described with reference to FIGS. 19A through 19D and 20A through 20D. Herein, a process in which a plug and a metal interconnect are formed by forming a via hole before forming an interconnect groove and filling a metal film in the via hole and the interconnect groove, namely, what is called via first process, will be described.
First, as shown in FIG. 19A, an insulating film 122 of, for example, a silicon oxide film is formed on a substrate (semiconductor wafer) 121 by, for example, the chemical vapor deposition method or the spin on dielectric method.
Next, as shown in FIG. 19B, a first resist pattern 123 having an opening for forming a via hole is formed on the insulating film 122 by the lithography, and thereafter, as shown in FIG. 19C, the insulating film 122 is dry etched by using the first resist pattern 123 as a mask, thereby forming a via hole 124 in the insulating film 122.
Then, as shown in FIG. 19D, after forming a bottom antireflection coating (BARC) 125 on the insulating film 122 including the inside of the via hole 124, a second resist pattern 126 having an opening for forming an interconnect groove is formed on the bottom antireflection coating 125.
Next, as shown in FIG. 20A, the bottom antireflection coating 125 is dry etched by using the second resist pattern 126 as a mask, so as to allow a portion of the bottom antireflection coating 125 to remain in a lower portion of the via hole 124. Thereafter, the insulating film 122 is dry etched by using the second resist pattern 126 and the bottom antireflection coating 125 as a mask, thereby forming an interconnect groove 127 in the insulating film 122.
Subsequently, as shown in FIG. 20B, after removing the second resist pattern 126 and the bottom antireflection coating 125 by ashing and cleaning, a barrier metal layer (not shown in the drawing) is formed by the sputtering method. Thereafter, as shown in FIG. 20C, a copper film 128 is deposited on the barrier metal layer by the plating method, so as to fill the via hole 124 and the interconnect groove 127 with the copper film 128.
Next, an unnecessary portion of the copper film 128, namely, a portion thereof exposed above the insulating film 122, is removed by the chemical mechanical polishing. Thus, as shown in FIG. 20D, a plug 130 and a metal interconnect 131 made of the copper film 128 are formed at the same time.